1. Field of the Invention
The present invention relates to non-volatile memory devices and particularly to an error detection method apparatus for use in the non-volatile memory devices.
2. Description of the Prior Art
Flash or non-volatile memory has gained wide acceptance for various applications and particularly its non-volatile characteristic in retaining information or data even when power is disconnected. This makes non-volatile memory especially well suited for non-volatile portable devices that may lose power. Some devices, which include flash memory are constructed from electrically-erasable programmable read-only memory (EEPROM) cells.
Rather than use a randomly-addressable scheme such as is common with dynamic-random-access memory (DRAM), many flash memory-based devices use a block-based addressing where a command and an address are transmitted via a data bus and then a block of information is read from or written to the flash memory. Since the data bus is also used to send commands and addresses, fewer pins are needed on the flash-memory chip thereby reducing cost. Thus, flash memory is often used as a mass-storage device rather than a randomly-addressable device.
Typically, in a flash memory device, a microcontroller is employed for controlling information transfer between the flash memory and a host of some type. The microcontroller typically includes ROM with a control program that is read by the internal central processing unit (CPU) of the microcontroller when the microcontroller is booted or powered up. Once initialized with the control program, the CPU can control data transfers between the serial interface and the flash controller.
A popular bus standard is a Multi-Media Card (MMC), the specifications of which are defined and adopted by the industry. An extension of MMC is known as Secure Digital (SD). Various other flash device interfaces such as Compact Flash (CF), Memory Stick (MS), PCI-Express (PCIE), ATA/IDE, and Serial ATA (SATA), etc, which are commonly employed in today's portable multimedia, computer, or communication devices as data storage elements. A controller coupled to the bus would also operationally conform to the foregoing standards.
With the advent of the popularity of flash memory, density of flash memory devices (or chips, integrated circuits or semiconductor) is increasing thereby increasing the rate of defect spots. Even more noteworthy is the increase in the rate of defect spots in Multi-Level Cell (MLC), which is a certain type of non-volatile memory, during the flash manufacturing process. Compared with a SLC process, random error bits in MLC processes occur more often due to multi-level threshold voltages (less noise margin) needed to detect logic levels.
An effective error detection results when using Bose, Ray-Chaudhuri, Hocquenghem (BCH) code. Therefore, an apparatus and method are needed for flash operations to improve the accuracy of information.
BCH codes are multiple error correcting utilizing block cyclic Galois codes to do the same. As described earlier, the BCH algorithm is popularly applied in the industry for random error correction purposes and as compared with Reed Solomon algorithms, another error coding/decoding scheme, it is more appropriate for burst error correction. Error location/detection is known to be one of the most difficult procedures associated with using BCH.
By way of brief background, a Berlekamp-Messay and Euclidian method is first applied to find roots of the error polynomial and then, Chien's method is applied to search for error locations. However, since both implementations require complex hardware and lengthy calculations, cost of error correction coding (ECC) is increased in the foregoing traditional methods.
A second method utilizes searching in look-up table. A pre-calculated value is stored in memory, such as ROM, for error searching. This method advantageously increases speed, because time is saved in performing calculations, however, for long size codes, ROM could occupy expensive silicon real estate and therefore directly increases controller chip cost.
What is needed is flash memory coding and decoding apparatus and method having advantageously lower complexity with simple control signal handling and faster calculation speed that is not influenced by code length.